By Ramesh K Choudhary, Jyotsna Kumar Mandal, Nitin Auluck, H A Nagarajaram
This ebook highlights a suite of high quality peer-reviewed learn papers offered on the 9th overseas convention on complicated Computing & verbal exchange applied sciences (ICACCT-2015) held at Asia Pacific Institute of data know-how, Panipat, India in the course of 27–29 November 2015. The ebook discusses a wide selection of business, engineering and clinical functions of the rising ideas. Researchers from academia and current their unique paintings and alternate rules, info, innovations and purposes within the box of complicated Computing and verbal exchange Technology.
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Additional resources for Advanced Computing and Communication Technologies: Proceedings of the 9th ICACCT, 2015
K. Choudhary et al. K. C. Lobo during designing the memory. Here we have done the analysis of various SRAM cells made of 6, 7, 8, 9 and 10 transistors, at transistor level to highlight the above mentioned issues. To reduce power dissipation various approaches can be adopted like changing the threshold voltage or lowering the supply voltage . But scaling the supply voltage effect the performance directly while scaling the threshold voltage shows highest impact in SNM . In this paper, we have reviewed different SRAM cells like 7T SRAM [3, 4], 8T SRAM [5, 6], 9T SRAM [7, 8] and 10T SRAM [9, 10] based on read/write delay, power consumption and SNM compare to conventional 6T SRAM cell [1, 11–13].
Xilinx Zynq provides three types of memory interface methods: GP (General Purpose), HP (High performance), and ACP (Accelerator Coherency Port). In the ﬁrst approach hardware accelerator is connected to ARM CPU located on Zynq through GP interface for memory access through DMA. This brings down the performance. In the next approach accelerator is connected to ARM CPU through HP port, which increases the performance because HP ports have direct connection with DDR memory controllers on Zynq PS. In the third approach accelerator is connected through ACP port which further increases the performance because through ACP DMA can access caches of ARM cores which in turn gives low latency.
We have proposed a strategy for ﬁnding lower bound at each level of the tree and also a strategy for tree pruning. These strategies allow us to explore a smaller portion of the search tree. We have proposed a strategy for obtaining upper bound which is able to achieve optimal results for a large number of standard graphs for which experiments have been performed. It has been clearly shown that BBVBMP outperforms the state-of-art exact method for VBMP. References 1. : A survey of graph layout problems.
Advanced Computing and Communication Technologies: Proceedings of the 9th ICACCT, 2015 by Ramesh K Choudhary, Jyotsna Kumar Mandal, Nitin Auluck, H A Nagarajaram
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